The present invention relates to a semiconductor device having a ferroelectric thin film to be used for, for example, an FERAM (ferroelectric random access memory) and a fabricating method therefor.
In recent years, there have energetically been conducted researches into a ferroelectric thin film for use in a semiconductor device. The semiconductor device having the ferroelectric thin film has energetically been examined and developed for the practical use thereof as a non-volatile memory capable of substituting for an EPROM (erasable programmable read only memory), an EEPROM (electrically erasable programmable read only memory) or a flash memory and as a memory capable of substituting for an SRAM (static random access memory) and a DRAM (dynamic random access memory) in terms of its high-speed write, read, low-voltage drive, satisfactory fatigue characteristic and so on.
The capacitor size is reduced by utilizing the high permittivity characteristic of the ferroelectric thin film, by which a gigabit-class device is fabricated by way of trial for the high-density integration of semiconductor devices such as DRAM's.
As described above, in order to apply the semiconductor device having the ferroelectric thin film to a variety of devices such as semiconductor devices, it is indispensable to develop a thin film forming technique of a ferroelectric material matched with the conventional semiconductor fabricating process. That is, the desired characteristics can be provided with a reduced film thickness by a reduction in the film forming temperature and the achievement of fine and flat configuration of the thin film, and it is demanded to develop a ferroelectric material capable of coping with micromachining and a reduction in an operating voltage as well as a thin film forming technique therefor.
Conventionally, there has been a semiconductor device having a ferroelectric capacitor constructed of a lower electrode, a ferroelectric thin film and an upper electrode, which are successively laminated onto a substrate. As a material for the ferroelectric thin film of this ferroelectric capacitor, there have been examined PZT (PbZrxTil−xO3) and SBT (SrBi2Ta2O9). The SBT has the advantage that the deterioration thereof due to film fatigue is less than that of PZT and the advantage that it permits low-voltage driving.
As a method for forming a film of SBT, it is general to use the MOD (metal organic decomposition) method, the sol-gel method, the MOCVD (metal organic chemical vapor deposition) method, the sputtering method or a similar method. According to the above-mentioned methods, the ferroelectric thin film is required to be subjected to heat treatment at a temperature of 600° C. to 800° C. in an oxidizing atmosphere is necessary for bringing out the ferroelectric characteristic.
A method for fabricating a semiconductor device having a ferroelectric thin film made of an SBT material will be described below.
First of all, as shown in FIG. 3A, a silicon oxide film 42 having a film thickness of 200 nm is formed by thermal oxidation on a surface of a silicon substrate 41, and thereafter, a Ti adhesion layer 43 having a film thickness of 30 nm and a Pt lower electrode 44 having a film thickness of 200 nm are successively formed by the sputtering method on the silicon oxide film 42. Then, an SBT solution of a composition ratio of Sr/Bi/Ta=8/24/20 is applied onto the Pt lower electrode 44, subjected to a drying process at a temperature of 250° C. for five minutes and then to crystallization annealing at a temperature of 600° C. to 800° C. for 10 minutes to 60 minutes in an oxygen atmosphere, forming an SBT layer 45. Subsequently, by repeating a fabricating method similar to that of the SBT layer 45 three times, SBT layers 46, 47 and 48 are successively formed on the SBT layer 45, producing a ferroelectric thin film 50 that has a film thickness of 200 nm and is constructed of the plurality of SBT layers 45, 46, 47 and 48. The temperatures of crystallization annealing of the SBT layers 45, 46, 47 and 48 are the same.
Finally, as shown in FIG. 3B, Pt laminated onto the dielectric thin film 50 is patterned by photolithography, forming a Pt upper electrode 49.
However, according to the above-mentioned semiconductor device fabricating method, when the crystallization annealing of the SBT layers 45, 46, 47 and 48 is performed at a temperature of 700° C. to 800° C., the ferroelectric characteristic is improved to increase the remanence. However, there is the problem that a gap of a pinhole or the like is increased and the symmetry of the hysteresis loop becomes worse, degrading the homogeneity of the ferroelectric capacitor.
On the other hand, uniform minute crystal grains can be obtained when crystallization annealing of the SBT layers 45, 46, 47 and 48 is performed at a temperature of 600° C. to 700° C. However, the remanence is small, and this means that the ferroelectric characteristic is not sufficiently brought out. Accordingly, there is the problem that the aforementioned ferroelectric capacitor cannot be used for a storage element.
According to the semiconductor device fabricating method of Japanese Patent Laid-Open Publication No. HEI 10-321809, crystallization annealing is performed at a temperature of 500° C. to 700° C. in a decompressed oxygen atmosphere of 10 Torr by means of a vacuum device. As a result, there is the problem that mass productivity is inferior to the case where the crystallization annealing is performed under the normal pressure because of the use of the vacuum device.